Over the years, computer chips have gotten smaller, thanks to advances in materials science and manufacturing technologies. This march of progress, the doubling of transistors on a microprocessor roughly every two years, is called Moore’s Law. But there’s one component of the chip-making process in need of an overhaul if Moore’s law is to continue: the chemical mixture called photoresist.
The Cray XC30 system will be used by a nation-wide consortium of scientists called the Indian...
How using CPU/GPU parallel computing is the next logical step - My work in...
IBM Announces $3B Research Initiative to Tackle Chip Grand Challenges for Cloud and Big Data SystemsJuly 9, 2014 4:58 pm | by IBM | News | Comments
IBM has announced it is investing $3 billion over the next five years in two broad research and...
The FirePro W8100 professional graphics card is designed to enable new levels of workstation performance delivered by the second-generation AMD Graphics Core Next (GCN) architecture. Powered by OpenCL, it is ideal for the next generation of 4K CAD (computing-aided design) workflows, engineering analysis and supercomputing applications.
Washington State University has developed a wireless network on a computer chip that could reduce energy consumption at huge data farms by as much as 20 percent.
AppliedMicro has announced the readiness of the X-Gene Server on a Chip based on the 64-bit ARMv8-Aarchitecture for High Performance Computing (HPC) workloads.
Eurotech has teamed up with AppliedMicro Circuits Corporation and NVIDIA to develop a new, original high performance computing (HPC) system architecture that combines extreme density and best-in-class energy efficiency. The new architecture is based on an innovative highly modular and scalable packaging concept.
For years, Li-Shiuan Peh has argued that the massively multicore chips of the future will need to resemble little Internets, where each core has an associated router, and data travels between cores in packets of fixed size. This week, at the International Symposium on Computer Architecture, Peh’s group unveiled a 36-core chip that features just such a “network-on-chip.”
Researchers at UCLA have created a nanoscale magnetic component for computer memory chips that could significantly improve their energy efficiency and scalability. The design brings a new and highly sought-after type of magnetic memory one step closer to being used in computers, mobile electronics such as smart phones and tablets, as well as large computing systems for big data.
Like a Formula One race car stuck in a traffic jam, HPC hardware performance is frequently hampered by HPC software. This is because some of the most widely used application codes have not been updated for years, if ever, leaving them unable to leverage advances in parallel systems. As hardware power moves toward exascale, the imbalance between hardware and software will only get worse. The problem of updating essential scientific ...
Solving some of the biggest challenges in society, industry and sciences requires dramatic increases in computing efficiency. Many HPC customers are sitting on incredible untapped compute reserves and they don’t even know it. The very people who are focused on solving the world’s biggest problems with high-performance computing are often only using a small fraction of the compute capability their systems provide. Why? Their software ...
The U.S. Department of Energy’s (DOE) National Energy Research Scientific Computing (NERSC) Center and Cray Inc. announced that they have signed a contract for a next generation of supercomputer to enable scientific discovery at the DOE’s Office of Science (DOE SC).
IBM has debuted new Power Systems servers that allow data centers to manage staggering data requirements with unprecedented speed, all built on an open server platform. In a move that sharply contrasts other chip and server manufacturers' proprietary business models, IBM released detailed technical specifications for its POWER8 processor, inviting collaborators and competitors alike to innovate on the processor and server platform
As modern computer systems become more powerful, utilizing as many as millions of processor cores in parallel, Intel is looking for new ways to efficiently use these high performance computing (HPC) systems to accelerate scientific discovery. As part of this effort, Intel has selected Georgia Tech as the site of one of its Parallel Computing Centers.
Matthew Tolentino is a Research Scientist at Intel and an Affiliate Assistant Professor at the University of Washington.
Thomas Wild's research interests include Many-core system on chip (SoC) architectures, Network processor (NPU) architectures, On-chip communication architectures, networks on chip (NoC), System level design methodologies, and Design space exploration.
The AMD FirePro W9100 professional graphics card is designed for next-generation 4K workstations accelerated by OpenCL (Open Computing Language). With up to 2.62 TFLOPS double precision of GPU compute power and ultra-high resolution multi-display capabilities, video, design and engineering professionals can utilize 16 GB of ultra-fast GDDR5 memory and multi-task across up to six 4K displays.
GE Intelligent Platforms has signed an agreement with NVIDIA to bring products based on the NVIDIA Tegra K1 mobile processor to the embedded computing market.
All signs indicate a healthy continuing demand for mobile technology that can support ever-more-demanding eye-candy and apps on very-high-resolution display devices. According to independent high performance computing expert Rob Farber, mobile tech is where the money is right now in computer technology.
Rackform iServ R456 is a server equipped with Intel Xeon E7-4800v2 processors, formerly named Ivy Bridge-EX. The server features four Intel Xeon E7-4800v2 processors and up to 96 DDR3 DIMMs, triple the memory of previous products based on Intel Xeon E7-4800 processors.
Encryption and nuclear weapons are two easily recognized examples where a combinatorial explosion is a sought after characteristic. In the software development world, combinatorial explosions are bad. In particular, it is far too easy to become lost in the minutia of writing code that can run efficiently on NVIDIA GPUs, AMD GPUs, x86, ARM and Intel Xeon Phi while also addressing the numerous compiler and user interface vagaries
The Intel Xeon processor E7 v2 family delivers capabilities to process and analyze large, diverse amounts of data to unlock information that was previously inaccessible. The processor family has triple the memory capacity of the previous generation processor family, allowing much faster and thorough data analysis.
The Center for Biotechnology (CeBiTec) at Bielefeld University has added TimeLogic’s latest J-series Field Programmable Gate Array (FPGA) hardware to their computational tools platform. TimeLogic’s DeCypher systems are designed to greatly increase the speed of sequence comparison by combining custom FPGA circuitry with optimized implementations of BLAST, Smith-Waterman, Hidden Markov Model and gene modeling algorithms.
Opteron 6338P and 6370P 12- and 16-core server processors, code named “Warsaw,” are designed for enterprise workloads. The processors feature the “Piledriver” core and are fully socket and software compatible with the existing AMD Opteron 6300 Series.
In this segment, we look at mobile technology. All signs indicate a healthy continuing demand for technology that can support ever-more-demanding eye-candy and apps on very-high-resolution display devices. According to independent high performance computing expert Rob Farber, mobile tech is where the money is right now in computer technology.
Silicon Mechanics has launched its 3rd Annual Research Cluster Grant program, in which the company will donate a complete high-performance computer cluster as part of a highly competitive research grant. The competition is open to all US and Canadian qualified post-secondary institutions, university-affiliated research institutions, non-profit research institutions, and researchers at federal labs with university affiliations.
GE Intelligent Platforms announced that it has received an order from the High Performance Systems Branch (RITB) of the US Air Force Research Laboratory (AFRL) Information Directorate (RI) for a HPEC (High Performance Embedded Computing) system that will enable the development and deployment of advanced neuromorphic architectures and algorithms for adaptive learning, large-scale dynamic data analytics and reasoning.
2U TwinPro and TwinPro2 2U servers are available in 2-node (TwinPro) and 4-node (TwinPro²) configurations optimized for high-end, high-density data center, cloud computing, enterprise, HPC and big data applications.
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